Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 48 of 88
NXP Semiconductors
LPC3152/3154
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
[2] Dependent on package type.
[3] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
9. Static characteristics
9.1 Digital die
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Typ Max Unit
All digital I/O pins
V
i
input voltage −0.5 - +3.6 V
V
o
output voltage −0.5 - +3.6 V
I
o
output current VDDE_IOC = 3.3 V - 4 - mA
Temperature values
T
j
junction temperature −40 25 125 °C
T
stg
storage temperature
[2]
−65 - +150 °C
T
amb
ambient temperature −40 +25 +85 °C
Electrostatic handling
V
ESD
electrostatic
discharge voltage
human body model
[3]
−500 - +500 V
machine model −100 - +100 V
charged device
model
-500- V
Table 13: Static characteristics
T
amb
= − 40 ° C to +85 ° C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply pins
V
DD(IO)
input/output supply
voltage
NAND flash controller
pads (SUP4) and LCD
interface (SUP8); 1.8 V
mode
1.65 1.8 1.95 V
NAND flash controller
pads (SUP4) and LCD
interface (SUP8); 3.3 V
mode
2.5 3.3 3.6 V
other peripherals
(SUP 3)
2.7 3.3 3.6 V
V
DD(CORE)
core supply voltage (SUP1) 1.1 1.2 1.3 V