Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 5 of 88
NXP Semiconductors
LPC3152/3154
5. Pinning information
5.1 Pinning
Fig 2. LPC3152/3154 pinning TFBGA208 package
002aae464
LPC3152/
LPC3154
Transparent top view
ball A1
index area
U
T
R
P
N
M
K
H
L
J
G
F
E
D
C
A
B
24681012
13
14
15 17
16
1357911
Table 3. Pin allocation table
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Row A
1 n.c. 2 EBI_A_1_CLE 3 EBI_D_9 4 VDDE_IOC
5 VSSE_IOC 6 VDDI 7 VSSI 8 SPI_MISO
9 I2C_SCL0 10 FFAST_IN 11 n.c. 12 n.c.
13 ADC10B_GNDA 14 VSSE_IOC 15 VDDE_IOC 16 HP_VDDA33
17 n.c. - - -
Row B
1 n.c. 2 n.c. 3 n.c. 4 n.c.
5 mNAND_RYBN0 6 mGPIO9 7 mGPIO6 8 SPI_MOSI
9 n.c. 10 FFAST_OUT 11 VDDA12 12 ADC10B_GPA0
13 ADC10B_VDDA33 14 n.c. 15 HP_FCR 16 HP_GNDA
17 HP_OUTL - - -
Row C
1 n.c. 2 EBI_D_10 3 n.c. 4 EBI_A_0_ALE
5 mNAND_RYBN1 6 mGPIO10 7 mGPIO7 8 SPI_SCK
9 VPP 10 I2C_SDA0 11 VSSA12 12 ADC10B_GPA2
13 ADC10B_GPA1 14 DAC_VDDA33 15 HP_OUTR 16 HP_FCL
17 PSU_PLAY - - -
Row D
1 VDDE_IOA 2 EBI_D_11 3 EBI_D_8 4 mNAND_RYBN3