Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 51 of 88
NXP Semiconductors
LPC3152/3154
[1] The parameter values specified are simulated values.
[1] On pin ADC10B_GNDA.
[2] Conditions: V
SSA
= 0 V on pin ADC10B_GNDA, V
DD(ADC)
=3.3V.
[3] The ADC is monotonic, there are no missing codes.
[4] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 14.
I
2
C0-bus pins
I
OZ
OFF-state output
current
V
O
= 0 V; V
O
=V
DD
;
no pull-up/down
- - 7.25 μA
V
IH
HIGH-level input
voltage
[1]
0.7VDDE_IOC - - V
V
IL
LOW-level input
voltage
[1]
- - 0.3VDDE_IOC V
V
hys
hysteresis voltage 0.1VDDE_IOC - - V
V
OL
LOW-level output
voltage
I
OLS
= 3 mA - - 0.298 V
I
LI
input leakage current VDDE voltage domain;
T
amb
= 25 °C
[1]
- 1.7 <tbd> μA
VDD voltage domain;
T
amb
= 25 °C
[1]
- 0.01 <tbd> μA
USB
V
i(cm)
common-mode input
voltage
high-speed mode −50 200 500 mV
full-speed/low-speed
mode
800 - 2500 mV
chirp mode −50 - 600 mV
V
i(dif)
differential input
voltage
100 400 1100 mV
Table 13: Static characteristics
T
amb
= − 40 ° C to +85 ° C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 14. Static characteristics of the 10 bit ADC
V
DD(ADC)
= 2.7 V to 3.6 V; T
amb
= − 40 ° C to +85 ° C unless otherwise specified; ADC frequency <tbd>.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0
[1]
-V
DD(ADC)
V
C
ia
analog input capacitance - - <tbd> pF
N
res(ADC)
ADC resolution 2 - 10 bit
E
D
differential linearity error
[2][3][4]
--±1LSB
E
L(adj)
integral non-linearity
[2][5]
--±1LSB
E
O
offset error
[2][6]
- - <tbd> LSB
E
G
gain error
[2][7]
--<tbd>%
E
T
absolute error
[2][8]
- - <tbd> LSB
V
err(O)
offset error voltage −20 - +20 mV
V
err(FS)
full-scale error voltage <tbd> - <tbd> mV
R
vsi
voltage source interface
resistance
--<tbd>kΩ