Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 55 of 88
NXP Semiconductors
LPC3152/3154
[1] Deviation of output voltage on pin PSU_VOUTn from its nominal, programmed value.
output PSU_VOUT2
V
O
output voltage generated from
PSU_VBAT
(programmable
in 8 levels)
0.9 1.04 1.4 V
generated from
PSU_VBUS
(LDO1 on)
1.15 1.2 1.25 V
ΔV
o
output voltage deviation output voltage
generated from
PSU_VBAT
[1]
−50 - +50 mV
I
O
output current on pin
PSU_VOUT2
--80mA
I
L(LDO)(max)
maximum LDO load current on LDO2 80 100 - mA
output PSU_VOUT3
V
O
output voltage generated from
either
PSU_VBAT or
PSU_VBUS
(programmable
in 2 levels)
-1.41.8V
on LDO3 of
V
O
= 1.4 V
(default)
1.35 1.4 1.45 V
on LDO3 of
V
O
= 1.8 V
(default)
1.75 1.8 1.85 V
I
O
output current on pin
PSU_VOUT3
-50mA
I
L(LDO)(max)
maximum LDO load current on LDO3 50 - mA
DC-to-DC converter
η
(DCDC)
DC-to-DC converter
efficiency
-85-%
f
clk
clock frequency - 12 - MHz
f
osc
oscillator frequency 8 10 12 MHz
f
sw
switching frequency - 1 - MHz
Table 16: Static characteristics of the PSU
…continued
T
amb
= − 40 ° C to +85 ° C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit