Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 6 of 88
NXP Semiconductors
LPC3152/3154
5 mNAND_RYBN2 6 mGPIO8 7 mGPIO5 8 SPI_CS_OUT0
9 SPI_CS_IN 10 PWM_DATA 11 GPIO4 12 GPIO3
13 n.c. 14 HP_OUTC 15 PSU_STOP 16 PSU_VSSA
17 PSU_VSSA_CLEAN - - -
Row E
1 VSSE_IOA 2 EBI_D_12 3 EBI_D_7 4 EBI_D_6
14 HP_VREF 15 RSTIN_N 16 PSU_VBAT 17 PSU_VOUT3
Row F
1 n.c. 2 EBI_D_13 3 EBI_D_5 4 EBI_D_4
14 TDO 15 DAC_VREFN 16 DAC_VREFP 17 PSU_VBAT2
Row G
1 n.c. 2 EBI_D_14 3 n.c. 4 EBI_D_3
14 PSU_VOUT2 15 VDDE_IOD 16 PSU_VIN1 17 PSU_LX2
Row H
1 VSSI 2 EBI_D_15 3 EBI_D_1 4 EBI_D_2
14 PSU_VOUT1 15 PSU_LX1 16 PSU_VSS1 17 PSU_VBAT1
Row J
1 VDDI 2 EBI_NCAS_BLOUT_0 3 EBI_D_0 4 EBI_NRAS_BLOUT_1
14 CHARGE_VBUS 15 CHARGE_VSS 16 PSU_VBUS 17 CHARGE_VNTC
Row K
1 VSSE_IOB 2 n.c. 3 EBI_DQM_0_NOE 4 EBI_NWE
14 RTC_BACKUP 15 CHARGE_CC_REF 16 CHARGE_VBAT 17 CHARGE_BAT_SENSE
Row L
1 VDDE_IOB 2 NAND_NCS_0 3 NAND_NCS_1 4 NAND_NCS_2
14 VSSE_IOD 15 RTC_VDD36 16 FSLOW_OUT 17 FSLOW_IN
Row M
1 VDDE_IOA 2 NAND_NCS_3 3 n.c. 4 CLOCK_OUT
14 VDDI_AD 15 VSSI_AD 16 RTC_INT 17 RTC_VSS
Row N
1 VSSE_IOA 2 USB_VDDA12_PLL 3 USB_VBUS 4 USB_RREF
14 ADC_VDDA33 15 ADC_VDDA18 16 ADC_GNDA 17 UOS_VSS
Row P
1 n.c. 2 USB_VSSA_REF 3 USB_ID 4 mLCD_DB_10
5 mLCD_DB_9 6 mLCD_DB_5 7 mLCD_E_RD 8 mLCD_DB_1
9 I2SRX_DATA0 10 UART_TXD 11 mUART_CTS_N 12 GPIO2
13 ADC_TINL 14 ADC_TINR 15 UOS_VBUS 16 UOS_VBAT
17 UOS_CX2 - - -
Row R
1 USB_DM 2 USB_VSSA_TERM 3 USB_VDDA33 4 mLCD_DB_15
5 mLCD_DB_6 6 mLCD_DB_3 7 mLCD_RS 8 mLCD_CSB
Table 3. Pin allocation table
…continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
Pin Symbol Pin Symbol Pin Symbol Pin Symbol