Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 60 of 88
NXP Semiconductors
LPC3152/3154
10. Dynamic characteristics
10.1 Digital die
10.1.1 LCD controller
10.1.1.1 Intel 8080 mode
[1] Timing is determined by the LCD Interface Control Register fields: INVERT_CS = 1; MI = 0; PS = 0;
INVERT_E_RD = 0. See the LPC315x user manual.
Table 21. Dynamic characteristics: LCD controller in Intel 8080 mode
C
L
=25pF, T
amb
= − 40 ° C to +85 ° C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
Symbol Parameter Conditions Min Typ Max Unit
t
su(A)
address set-up time - 1 × LCDCLK - ns
t
h(A)
address hold time - 2 × LCDCLK - ns
t
cy(a)
access cycle time
[1]
-5 × LCDCLK - ns
t
w(en)W
write enable pulse width
[1]
-2 × LCDCLK - ns
t
w(en)R
read enable pulse width
[1]
-2 × LCDCLK - ns
t
r
rise time 2 - 5 ns
t
f
fall time 2 - 5 ns
t
su(D)
data input set-up time <tbd> - - ns
t
h(D)
data input hold time <tbd> - - ns
t
d(QV)
data output valid delay time - −1 × LCDCLK - ns
t
dis(Q)
data output disable time - 2 × LCDCLK - ns
Fig 18. LCD timing (Intel 8080 mode)
002aae207
mLCD_RS
mLCD_CSB
mLCD_RW_WR,
mLCD_E_RD
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:12] (4 bit mode)
mLCD_DB[15:0] (16 bit mode),
mLCD_DB[15:8] (8 bit mode),
mLCD_DB[15:12] (4 bit mode)
t
h(A)
t
su(A)
t
w(en)R
and t
w(en)W
t
d(QV)
t
dis(Q)
t
su(D)
t
h(D)
t
f
t
r
t
cy(a)
read access
write access