Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 62 of 88
NXP Semiconductors
LPC3152/3154
10.1.1.3 Serial mode
[1] Timing is determined by the LCD Interface Control Register fields: PS = 1; SERIAL_CLK_SHIFT = 3;
SERIAL_READ_POS = 3. See the LPC315x user manual.
Table 23. Dynamic characteristics: LCD controller serial mode
C
L
=25pF, T
amb
= − 40 ° C to +85 ° C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
Symbol Parameter Conditions Min Typ Max Unit
T
cy(clk)
clock cycle time
[1]
-5 × LCDCLK - ns
t
w(clk)H
HIGH clock pulse width
[1]
-3 × LCDCLK - ns
t
w(clk)L
LOW clock pulse width
[1]
-2 × LCDCLK - ns
t
r
rise time 2 - 5 ns
t
f
fall time 2 - 5 ns
t
su(A)
address set-up time - 3 × LCDCLK - ns
t
h(A)
address hold time - 2 × LCDCLK - ns
t
su(D)
data input set-up time <tbd> - - ns
t
h(D)
data input hold time <tbd> - - ns
t
su(S)
chip select set-up time - 3 × LCDCLK - ns
t
h(S)
chip select hold time - 1 × LCDCLK - ns
t
d(QV)
data output valid delay time - −1 × LCDCLK - ns
Fig 20. LCD timing (serial mode)
002aae209
mLCD_CSB
mLCD_RS
mLCD_DB13
(serial clock)
mLCD_DB14
(serial data in)
mLCD_DB15
(serial data out)
t
su(D)
t
su(A)
t
h(A)
t
su(S)
t
h(S)
t
h(D)
t
d(QV)
t
dis(Q)
t
f
t
r
t
w(clk)L
t
w(clk)H
T
cy(clk)