Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 63 of 88
NXP Semiconductors
LPC3152/3154
10.1.2 SRAM controller
[1] Refer to the LPC315x user manual for the programming of WAITOEN and HCLK.
[2] Refer to the LPC315x user manual for the programming of WAITRD and HCLK.
[3] (WAITRD − WAITOEN + 1) = 3 min at 60 MHz.
[4] Refer to the LPC315x user manual for the programming of WAITWEN and HCLK.
[5] Refer to the LPC315x user manual for the programming of WAITWR and HCLK.
[6] (WAITWD − WAITWEN + 1) = 3 min at 60 MHz.
Table 24. Dynamic characteristics: static external memory interface
C
L
=25pF, T
amb
= − 40 ° C to +85 ° C, unless otherwise specified; V
DD(IO)
= 1.8 V and 3.3 V (SUP8).
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
t
CSLAV
CS LOW to address valid
time
−1.8 0 4 ns
Read cycle parameters
t
OELAV
OE LOW to address valid
time
[1]
-0− WAITOEN × HCLK - ns
t
BLSLAV
BLS LOW to address valid
time
[1]
-0− WAITOEN × HCLK - ns
t
CSLOEL
CS LOW to OE LOW time - 0 + WAITOEN × HCLK - ns
t
CSLBLSL
CS LOW to BLS LOW time
[1]
- 0 + WAITOEN × HCLK - ns
t
OELOEH
OE LOW to OE HIGH time
[1][2][3]
-(WAITRD− WAITOEN + 1) × HCLK - ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[1][2][3]
-(WAITRD− WAITOEN + 1) × HCLK - ns
t
su(D)
data input set-up time 9 - - ns
t
h(D)
data input hold time - 0 - ns
t
CSHOEH
CS HIGH to OE HIGH time 3 0 - ns
t
CSHBLSH
CS HIGH to BLS HIGH time - 0 - ns
t
OEHANV
OE HIGH to address invalid
time
10 - - ns
t
BLSHANV
BLS HIGH to address invalid
time
-1× HCLK - ns
Write cycle parameters
t
CSLDV
CS LOW to data valid time - - 9 ns
t
CSLWEL
CS LOW to WE LOW time
[4]
-(WAITWEN+1)× HCLK - ns
t
CSLBLSL
CS LOW to BLS LOW time
[4]
- WAITWEN × HCLK - ns
t
WELDV
WE LOW to data valid time
[4]
-0− (WAITWEN + 1) × HCLK - ns
t
WELWEH
WE LOW to WE HIGH time
[4][5][6]
-(WAITWR− WAITWEN + 1) × HCLK - ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[4][5]
-(WAITWR− WAITWEN + 3) × HCLK - ns
t
WEHANV
WE HIGH to address invalid
time
-1× HCLK - ns
t
WEHDNV
WE HIGH to data invalid time - 1 × HCLK - ns
t
BLSHANV
BLS HIGH to address invalid
time
-1× HCLK - ns
t
BLSHDNV
BLS HIGH to data invalid
time
-1× HCLK - ns