Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 65 of 88
NXP Semiconductors
LPC3152/3154
10.1.3 SDRAM controller
Fig 22. External memory write access to static memory
t
BLSLBLSH
t
CSLAV
t
CSLDV
t
WEHANV
t
CSLWEL
t
CSLBLSL
t
WEHDNV
t
BLSHDNV
t
BLSHANV
t
WELWEH
t
WELDV
002aae162
EBI_NSTCS_X
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_A_[15:0]
EBI_D_[15:0]
EBI_NWE
Table 25. Dynamic characteristics of SDR SDRAM memory interface
T
amb
= − 40 ° C to +85 ° C, unless otherwise specified.
[1][2][3]
Symbol Parameter Conditions Min Typical Max Unit
f
oper
operating frequency
[4]
-80 90 MHz
T
CLCL
clock cycle time 11.1 <tbd> - ns
t
CLCX
clock LOW time - 5.55 - ns
t
CHCX
clock HIGH time - 5.55 - ns
t
d(o)
output delay time on pin EBI_CKE
[5]
-- 3.6 ns
on pins
EBI_NRAS_BLOUT,
EBI_NCAS_BLOUT,
EBI_NWE,
EBI_NDYCS
-- 3.6 ns
on pins EBI_DQM_1,
EBI_DQM_0_NOE
-- 5 ns