Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 71 of 88
NXP Semiconductors
LPC3152/3154
Fig 26. SPI master timing (CPHA = 1)
Fig 27. SPI master timing (CPHA = 0)
SCK (CPOL = 0)
MOSI
MISO
002aad986
t
SPICLK
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPISEDV
DATA VALID DATA VALID
t
SPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID
SCK (CPOL = 0)
MOSI
MISO
002aad987
t
SPICLK
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
DATA VALID DATA VALID
t
SPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID
t
SPISEDV