Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 75 of 88
NXP Semiconductors
LPC3152/3154
10.2.4 I
2
C-bus
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance C
b
in pF, from 10 pF to 400 pF.
Fig 32. I
2
S-bus timing (input)
002aad993
I2SRX_SCK
I2SRX_SDA
I2SRX_WS
T
cy
t
f
t
r
t
WH
t
su(D)
t
hD)
t
su(D)
t
h2
t
WL
Table 31. Dynamic characteristic: I
2
C-bus pins
T
amb
= − 40 ° C to +85 ° C.
[1]
Symbol Parameter Conditions Min Typ
[2]
Max Unit
f
SCL
SCL clock frequency Standard mode 0 <tbd> 100 kHz
Fast mode 0 <tbd> 400 kHz
t
f(o)
output fall time V
IH
to V
IL
20 + 0.1 × C
b
[3]
--ns
t
r
rise time Standard mode <tbd> <tbd> 1000 ns
Fast mode 20 + 0.1 × C
b
[3]
<tbd> 300 ns
t
f
fall time Standard mode <tbd> <tbd> 300 ns
Fast mode 20 + 0.1 × C
b
[3]
<tbd> 300 ns
t
BUF
bus free time between a STOP and
START condition
- <tbd> <tbd> <tbd>
t
LOW
LOW period of the SCL clock Standard mode 4.7 <tbd> <tbd> μs
Fast mode 1.3 <tbd> <tbd> μs
t
HD;STA
hold time (repeated) START
condition
- <tbd> <tbd> <tbd>
t
HIGH
HIGH period of the SCL clock Standard mode 4.0 <tbd> <tbd> μs
Fast mode 0.6 <tbd> <tbd> μs
t
SU;DAT
data set-up time Standard mode 250 <tbd> <tbd> ns
Fast mode 100 <tbd> <tbd> ns
t
SU;STA
set-up time for a repeated START
condition
- <tbd> <tbd> <tbd>
t
SU;STO
set-up time for STOP condition Standard mode 4.0 <tbd> <tbd> μs
Fast mode 0.6 <tbd> <tbd> μs