Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 9 of 88
NXP Semiconductors
LPC3152/3154
JTAG
JTAGSEL U10 SUP3 DI / GPIO I:PD DIO1 JTAG selection. Controls which digital die
TAP controller is configured in the JTAG chain
along with the analog die TAP controller. Must
be LOW during power-on reset.
TDI T10 SUP3 DI / GPIO I:PU DIO1 JTAG data Input
TRST_N U11 SUP3 DI / GPIO I:PD DIO1 JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
TCK U12 SUP3 DI / GPIO I:PD DIO1 JTAG clock input
TMS U9 SUP3 DI / GPIO I:PU DIO1 JTAG mode select input
TDO F14 SUP3 DO Z DIO2 JTAG data output
UART
mUART_CTS_N
[4][6]
P11 SUP3 DI / GPIO I DIO1 UART Clear-To-Send (CTS) (active LOW)
mUART_RTS_N
[4][6]
R11 SUP3 DO / GPIO O DIO1 UART Ready-To-Send (RTS) (active LOW)
UART_RXD
[4]
R10 SUP3 DI / GPIO I DIO1 UART serial input
UART_TXD
[4]
P10 SUP3 DO / GPIO O DIO1 UART serial output
I
2
C master/slave interface
I2C_SDA0 C10 SUP3 DIO I IICD I
2
C-bus data line
I2C_SCL0 A9 SUP3 DIO I IICC I
2
C-bus clock line
Serial Peripheral Interface (SPI)
SPI_CS_OUT0
[4]
D8 SUP3 DO O DIO4 SPI chip select output (master)
SPI_SCK
[4]
C8 SUP3 DIO I DIO4 SPI clock input (slave) / clock output (master)
SPI_MISO
[4]
A8 SUP3 DIO I DIO4 SPI data input (master) / data output (slave)
SPI_MOSI
[4]
B8 SUP3 DIO I DIO4 SPI data output (master) / data input (slave)
SPI_CS_IN
[4]
D9 SUP3 DI I DIO4 SPI chip select input (slave)
Digital power supply
VDDI J1;
U13;
A6
SUP1 Supply CS2 Digital core supply
VDDI_AD M14 SUP2 Supply CS2 Core supply for digital logic on analog die -
has to be connected to 1.4/1.8 V rail
VSSI H1;
U14;
A7
- Ground CG2 Digital core ground
VSSI_AD M15 - Ground CG2 Digital core ground of analog die
Peripheral power supply
VDDE_IOA D1;
M1
SUP4 Supply PS1 Peripheral supply NAND flash controller
VDDE_IOB L1;
U7
SUP8 Supply PS1 Peripheral supply LCD interface / SDRAM
interface
Table 4. Pin description
…continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
TFBGA pin name TFB
GA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description