Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 296 (15x15) 16/32-Bit 266 MHz I/O number 51

1. General description

The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high

performance applications. NXP achieved their performance goals using a 90 nanometer

process to implement an ARM926EJ-S CPU core with a vector floating point co-processor

and a large set of standard peripherals including USB On-The-Go. The

LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.

The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,

5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides

the virtual memory capabilities needed to support the multi-programming demands of

modern operating systems. The ARM926EJ-S also has a hardware based set of DSP

instruction extensions, which includes single cycle MAC operations, and hardware based

native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB

instruction cache and a 32 kB data cache.

For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced

technology development to optimize intrinsic power and uses software controlled

architectural enhancements to optimize application based power management.

The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash

interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an

external bus interface that supports SDR and DDR SDRAM as well as static devices. In

addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,

two I

C-bus interfaces, two SPI/SSP ports, two I

S-bus interfaces, two single output

PWMs, a motor control PWM, six general purpose timers with capture inputs and compare

outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)

with a touch screen sense option.

For additional documentation, see Section 15 “

References”.

2. Features and benefits

 ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.

 Vector Floating Point (VFP) coprocessor.

 32 kB instruction cache and 32 kB data cache.

 Up to 256 kB of Internal SRAM (IRAM).

 Selectable boot-up from various external devices: NAND flash, SPI memory, USB,

UART, or static memory.

LPC3220/30/40/50

16/32-bit ARM microcontrollers; hardware floating-point

coprocessor, USB On-The-Go, and EMC memory interface

Rev. 2.1 — 24 June 2014 Product data sheet

Summary of content (80 pages)

PAGE 1
LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 2.1 — 24 June 2014 Product data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go.
PAGE 2
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers  Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time.
PAGE 3
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers          Six enhanced timer/counters which are architecturally identical except for the peripheral base address. Two capture inputs and two match outputs are pinned out to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs.  32-bit millisecond timer driven from the RTC clock.
PAGE 4
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 4. Ordering information Table 1.
PAGE 5
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 5.
PAGE 6
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 6. Pinning information 6.1 Pinning ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 18 11 13 15 17 A B C D E F G H J K L M N P R T U V 002aae398 Transparent top view Fig 2. Table 3.
PAGE 7
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 3.
PAGE 8
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 3.
PAGE 9
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 3.
PAGE 10
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 6.2 Pin description Table 4. Pin description Symbol Pin Power supply domain Type Description ADIN0/TS_YM U15 VDD_AD analog in ADC input 0/touch screen Y minus ADIN1/TS_XM T14 VDD_AD analog in ADC input 0/touch screen X minus ADIN2/TS_AUX_IN V16 VDD_AD analog in ADC input 2/touch screen AUX input DBGEN G14 VDD_IOD I: PD Device test input LOW = JTAG in-circuit debug available; normal operation.
PAGE 11
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 12
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 13
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 14
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 15
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 16
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 17
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 18
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 19
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 20
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4.
PAGE 21
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4. Pin description …continued Symbol Pin VDD_IOC Power supply domain Type Description F7, VDD_IOC G6, H6, J5 power 1.8 V or 3.3 V supply for IOC domain VDD_IOD F13, F9 VDD_IOD power 1.8 V to 3.3 V supply for IOD domain VDD_OSC T18 VDD_OSC power 1.2 V supply for main oscillator VDD_PLL397 T16 VDD_PLL397 power 1.2 V supply for 397x PLL VDD_PLLHCLK R17 VDD_PLLHCLK power 1.
PAGE 22
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 4. Pin description …continued Symbol Pin Power supply domain Type Description VSS_PLLUSB R16 - power Ground for USB PLL VSS_RTCCORE L14 - power Ground for RTC VSS_RTCOSC P18 - power Ground for RTC oscillator [1] The PWM2_CTRL register controls this pin function (see LPC32x0 User manual). Table 5. Digital I/O pad types[1] Parameter Abbreviation I/O type I = input. O = output. I/O = bidirectional.
PAGE 23
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 6. Supply domains Supply domain Voltage range Related supply pins Description VDD_IOA[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOA Peripheral supply. VDD_IOB[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOB Peripheral supply. VDD_IOC[1] 1.7 V to 1.95 V or 2.3 V to 3.6 V VDD_IOC Peripheral supply. VDD_IOD[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOD Peripheral supply.
PAGE 24
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor.
PAGE 25
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048  24 bits captures the trace information under software debugger control. Data from the ETB is recovered by the debug software through the JTAG port.
PAGE 26
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions. A write access to FAB peripherals takes a single AHB clock and a read access to FAB peripherals takes two AHB clocks.
PAGE 27
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 4.0 GB 0xFFFF FFFF RESERVED 0xE400 0000 0xE3FF FFFF 0xE300 0000 0xE2FF FFFF 0xE200 0000 0xE1FF FFFF 0xE100 0000 0xE0FF FFFF 0xE000 0000 0xDFFF FFFF EMC_CS3 EMC_CS2 EMC_CS1 EMC_CS0 off-chip memory RESERVED 0xC000 0000 0xBFFF FFFF EMC_DYCS1 0xA000 0000 0x9FFF FFFF EMC_DYCS0 0x8000 0000 0x7FFF FFFF 2.0 GB RESERVED 0x5000 0000 0x4FFF FFFF RESERVED peripherals on AHB matrix slave port 7 1.
PAGE 28
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.4 Internal memory 7.4.1 On-chip ROM The built-in 16 kB ROM contains a program which runs a boot procedure to load code from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1).
PAGE 29
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error. 7.5.2 SD card controller The SD interface allows access to external SD memory cards.
PAGE 30
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers – extended wait • Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK. • Dynamic memory self-refresh mode supported by software. • Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset.
PAGE 31
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.
PAGE 32
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features 7.6.3.2 • • • • • Fully compliant with USB 2.0 full-speed specification. • • • • • • RAM message buffer size based on endpoint realization and maximum packet size. Supports 32 physical (16 logical) endpoints.
PAGE 33
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. • Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG specification compliant ATX. 7.6.
PAGE 34
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources.
PAGE 35
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically.
PAGE 36
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). 7.7.4.4 Power control modes The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption.
PAGE 37
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. Features • • • • • Each standard UART has 64 byte Receive and Transmit FIFOs. Receiver FIFO trigger points at 16, 32, 48, and 60 Bytes.
PAGE 38
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. 7.8.2.1 Features • • • • • • • • • • • • Supports slaves compatible with SPI modes 0 to 3.
PAGE 39
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses it to be come a slave-transmitter, a second source of data is needed.
PAGE 40
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals.
PAGE 41
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard of up to 64 keys in an 8  8 matrix. In operation, the keyboard scanner’s internal state machine will normally be in an idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed.
PAGE 42
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages, as a way to startup after power has been removed. The RTC block is implemented in a separate voltage domain.
PAGE 43
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter. The high-speed timer includes three match registers that are compared to the timer/counter value.
PAGE 44
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers • • • • • 32-bit pulse-width (match) register 10-bit dead-time register and an associated 10-bit dead-time counter 32-bit capture register Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/50 is a general purpose ARM926EJ-S 32-bit microprocessor with a 32 kB instruction cache and a 32 kB data cache.
PAGE 45
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V2) VDD(EMC) Parameter Conditions Notes Min Max Unit supply voltage (1.2 V) [2] 0.5 +1.4 V external memory controller supply voltage [3] 0.5 +4.6 V [4] 0.5 +4.6 V [5] 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.
PAGE 46
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 10. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol VDD(1V2) VDD(EMC) VDD(IO) Min Typ[1] Max Unit core supply voltage for full performance; 266 MHz (see Figure 4); VDD_CORE supply domain [2] 1.31 1.35 1.39 V core supply voltage for normal performance; 208 MHz (see Figure 4); VDD_CORE supply domain [2] 1.1 1.2 1.
PAGE 47
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit I-cache/D-cache, MMU enabled; CPU clock = 208 MHz; VDD_CORE = 1.2 V - 150 - mA I-cache/D-cache, MMU enabled; CPU clock = 266 MHz; VDD_CORE = 1.35 V - 218 - mA I-cache/D-cache, MMU disabled; CPU clock = 208 MHz; VDD_CORE = 1.
PAGE 48
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IDD(RTC) Parameter RTC supply current Min Typ[1] Max Unit normal operation; VDD_RTC = VDD_RTCCORE = VDD_RTCOSC = 1.2 V; Tamb = 25 C [8] - 13 - A RTC back up operation; [9] - 30 - A [9] - 4 - for HCLK; PLL output frequency = 266 MHz; VDD_PLLHCLK = 1.2 V - 2 - mA for USB; VDD_PLLUSB = 1.
PAGE 49
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 0 - VDD(IO) V Output pins and I/O pins configured as output VO [10][11] output voltage [12][13] VOH VOL IOH 1.8 V outputs; IOH = 1 mA [14] VDD(IO)  0.4 - - V 3.3 V outputs; IOH = 4 mA [14] VDD(IO)  0.4 - - V LOW-level output voltage 1.
PAGE 50
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(EMC) 23 51 93 A 3.3 V inputs with pull-down; VI = VDD(EMC) 73 155 266 A Excluding bonding pad capacitance - - 2.
PAGE 51
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Ci input capacitance Excluding bonding pad capacitance - - 1.6 pF VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14] - - 0.4 V 3.3 V outputs; IOL = 4 mA [14] - - 0.4 V [10][14] 3 - - mA IOL LOW-level output current VDD(IO) = 1.8 V; VOL = 0.
PAGE 52
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit HIGH-level input current VI = VDD; no pull-down [10] - - 1 A IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down [10] - - 1 A Ilatch I/O latch-up current [10] - - 100 mA Symbol IIH [1] Parameter Conditions (1.5VDD) < VI < (1.5VDD) Typical ratings are not guaranteed.
PAGE 53
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 10.1 Minimum core voltage requirements Figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50. 002aae872 1.4 VDD_CORE (V) 1.2 1.0 0.8 160 200 240 280 core frequency (MHz) Fig 4. Minimum required core supply voltage for different core frequencies 10.
PAGE 54
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 10.4 Power consumption in Run mode Power consumption is shown in Figure 5 for WinCE applications running under typical conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on but not used. I2S-interface (channel 1), LCD, SLC NAND controller, I2C1-bus, SD card, touchscreen ADC, and UART 3 are turned on. All other peripherals are turned off.
PAGE 55
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 10.5 ADC static characteristics Table 10. ADC static characteristics VDDA(3V3) = 3.3 V; Tamb = 25C unless otherwise specified; ADC clock frequency 4.5 MHz. Symbol Parameter VIA analog input voltage Cia analog input capacitance ED differential linearity error Conditions Min Typ Max Unit 0 - VDDA(3V3) V - - 1 pF [1][2][3] - 0.5 1 LSB integral non-linearity [1][4] - 0.
PAGE 56
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aae434 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
PAGE 57
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11. Dynamic characteristics 11.1 Clocking and I/O port pins Table 11. Dynamic characteristics Tamb = 40 C to +85 C, unless otherwise specified.
PAGE 58
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 12. Dynamic characteristics: static external memory interface …continued CL = 25 pF, Tamb = 20 C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V.
PAGE 59
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers EMC_A[23:0] tCSLAV EMC_CS[3:0] tCSLDV tWELDV EMC_D[31:0] tCSLWEL tWEHDNV tWEHANV tWELWEH EMC_WR tCSLBLSL tBLSHDNV tBLSHANV tBLSLBLSH EMC_BLS[3:0] 002aae469 Fig 8. External memory write access LPC3220_30_40_50 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 24 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
PAGE 60
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11.3 SDR SDRAM Controller Table 13. EMC SDR SDRAM memory interface dynamic characteristics CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified.[1][3] Symbol Parameter Min [4] Typical[2] Max Unit 104 133 MHz foper operating frequency tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 4.8 - ns tCH CK HIGH-level width - 4.8 - ns - (CMD_DLY  0.25) + 2.7 - (CMD_DLY  0.25) + 3.
PAGE 61
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11.4 DDR SDRAM controller Table 14. EMC DDR SDRAM memory interface dynamic characteristics[1] CL = 25 pF, Tamb = 25 C, unless otherwise specified. Symbol Parameter foper operating frequency Conditions Min Typical Max Unit - 104 133 MHz tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 0.5  tCK - ns tCH CK HIGH-level width - 0.5  tCK - ns control valid delay time [2][3] - (CMD_DLY  0.25) + 1.
PAGE 62
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers tCK tCH tCL EMC_CLK td(AV); td(V)ctrl EMC control and address signals th(A); th(ctl) valid 002aae436 Fig 10. DDR control timing parameters EMC_CLK command tDSS tDSH tDQSL tDQSH WRITE tDQSS EMC_DQS[1:0] tsu(Q) th(Q) EMC_D[31:0], EMC_DQM[3:0] 002aae437 Fig 11.
PAGE 63
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11.5 USB controller Table 15. Dynamic characteristics USB digital I/O pins VDD(IO) = 3.3 V; Tamb = 40 C to +85 C, unless otherwise specified.
PAGE 64
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Tcy(clk) MS_SCLK td(QV) th(Q) MS_BS (O) MS_DIO[3:0](O) tsu(D) th(D) MS_BS (I) MS_DIO[3:0] (I) 002aae441 Fig 14. SD card pin interface timing 11.7 MLC NAND flash memory controller Table 17. Dynamic characteristics of the MLC NAND flash memory controller Tamb = 40 C to +85 C.
PAGE 65
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers FLASH_CE tWC tWP tWH FLASH_WR D0 FLASH_IO[7:0] D1 Dn 10h tWB FLASH_RDY (R/B) 002aae442 Fig 15. MLC NAND flash controller write timing (writing to NAND flash) FLASH_CE tRC tCELREL tRP tREH FLASH_RD tRHZ D0 FLASH_IO[7:0] D1 D2 D3 002aae443 Fig 16. MLC NAND flash controller read timing (reading from NAND flash) 11.8 SLC NAND flash memory controller Table 18.
PAGE 66
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C.
PAGE 67
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C.
PAGE 68
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers tALS tALH tALS tALH FLASH_ALE tCLS tCLH tCLS FLASH_CLE FLASH_RDY tWB tWP tWP tWH FLASH_WR tRR tAR tRP tREH tRC tRHOH FLASH_RD tCLR tDS FLASH_IO[7:0] tDH command tCS tCH tDS tDH tDS tDH address tCS D0 tRHZ tREA D1 tCEA D2 D3 tCOH FLASH_CE command address data 002aae445 Fig 18.
PAGE 69
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers tCS tCH tCLS tCLH tCEA tCOH FLASH_CE tCLR FLASH_CLE tWP FLASH_WR FLASH_RD tWHR tRHOH tDS FLASH_IO[7:0] tDH tRHZ 70 h status tIR tREA command data 002aae446 Fig 19. MLC NAND flash memory status timing 11.9 SPI and SSP Controller 11.9.1 SPI Table 19. Dynamic characteristics of SPI pins on SPI master controller Tamb = 40 C to +85 C.
PAGE 70
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) TSPICYC tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIQV SPI1/2_DATAIO or MOSI0/1 tSPIOH DATA VALID DATA VALID tSPIDSU SPI1/2_DATAIN or MISO0/1 DATA VALID tSPIDH DATA VALID 002aae457 Fig 20.
PAGE 71
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers TSPICYC tSPICLKH tSPICLKL SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) tSPIDSU SPI1/2_DATAIO or MOSI0/1 DATA VALID tSPIDH DATA VALID tSPIQV SPI1/2_DATAIN or MISO0/1 tSPIOH DATA VALID DATA VALID 002aae458 Fig 22.
PAGE 72
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers VDD_IOD +3.3 V HDR-1x02 10 kΩ LPC32x0 10 kΩ 10 kΩ 10 kΩ 10 kΩ 33 Ω 1 JTAG_NTRST JTAG_nTRST JTAG_TDI JTAG_TDI JTAG_TDI JTAG_TMS JTAG_TMS JTAG_TMS JTAG_TCK JTAG_TCK JTAG_TCK JTAG_RTCK JTAG_RTCK JTAG_TDO JTAG_TDO JTAG_nTRST JTAG_RTCK JTAG_TDO JTAG_nSRST JTAG_nSRST VDD_RTC 1 JTAG_DBGRQ 3 JTAG_DBGACK BAT54C.
PAGE 73
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 13.
PAGE 74
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 14. Abbreviations Table 20.
PAGE 75
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Table 20. Abbreviations …continued Acronym Description UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus VFP Vector Floating Point processor 15. References LPC3220_30_40_50 Product data sheet [1] LPC3220/30/40/50 User manual UM10326: http://www.nxp.com/documents/user_manual/UM10326.pdf [2] LPC3220/30/40/50 Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC3250.
PAGE 76
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 16. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3220_30_40_50 v.2.1 20140624 Product data sheet CIN 201110012I LPC3220_30_40_50 v.2 Modifications: Section 12.1 “Connecting the JTAG_NTRST pin” added. LPC3220_30_40_50 v.2 20111020 Modifications: LPC3220_30_40_50 v.1 LPC3220_30_40_50 Product data sheet Product data sheet - LPC3220_30_40_50 v.
PAGE 77
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 78
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 79
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.3.1 7.1.3.2 7.2 7.2.1 7.2.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.2 7.5.2.1 7.5.3 7.6 7.6.1 7.6.2 7.6.2.1 7.6.3 7.6.3.1 7.6.3.2 7.6.3.3 7.6.4 7.6.4.1 7.7 7.7.1 7.7.2 7.7.2.1 7.7.3 7.7.3.1 7.7.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . .
PAGE 80
LPC3220/30/40/50 NXP Semiconductors 16/32-bit ARM microcontrollers 11.4 11.5 11.6 11.7 11.8 11.9 11.9.1 11.9.2 12 12.1 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 DDR SDRAM controller . . . . . . . . . . . . . . . . . USB controller . . . . . . . . . . . . . . . . . . . . . . . . Secure Digital (SD) card interface . . . . . . . . . MLC NAND flash memory controller. . . . . . . . SLC NAND flash memory controller . . . . . . . . SPI and SSP Controller . . . . . . . . . . . . . . . . . SPI . . . . . . . . . .