Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 2 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
 Multi-layer AHB system that provides a separate bus for each AHB master, including
both an instruction and data bus for the CPU, two data busses for the DMA controller,
and another bus for the USB controller, one for the LCD, and a final one for the
Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
 External memory controller for DDR and SDR SDRAM as well as for static devices.
 Two NAND flash controllers: One for single-level NAND flash devices and the other for
multi-level NAND flash devices.
 Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting
74 interrupt sources.
 Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be
used with the SD card port, the high-speed UARTs, I
2
S-bus interfaces, and SPI
interfaces, as well as memory-to-memory transfers.
 Serial interfaces:
 10/100 Ethernet MAC with dedicated DMA Controller.
 USB interface supporting either device, host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock.
 Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UARTs supports IrDA.
 Three additional high-speed UARTs intended for on-board communications that
support baud rates up to 921 600 when using a 13 MHz main oscillator. All
high-speed UARTs provide 64 byte FIFOs.
 Two SPI controllers.
 Two SSP controllers.
 Two I
2
C-bus interfaces with standard open-drain pins. The I
2
C-bus interfaces
support single master, slave, and multi-master I
2
C-bus configurations.
 Two I
2
S-bus interfaces, each with separate input and output channels. Each
channel can be operated independently on three pins, or both input and output
channels can be used with only four pins and a shared clock.
 Additional peripherals:
 LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024  768.
 Secure Digital (SD) memory card interface, which conforms to the SD Memory
Card Specification Version 1.01.
 General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24
GP output pins, and 51 GP I/O pins.
 10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from
three pins. Optionally, the ADC can operate as a touch screen controller.
 Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.
NXP implemented the RTC in an independent on-chip power domain so it can
remain active while the rest of the chip is not powered. The RTC also includes a
32-byte scratch pad memory.
 32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer
includes one external capture input pin and a capture connection to the RTC clock.
Interrupts may be generated using three match registers.