Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 26 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.2.1 APB
Many peripheral functions are accessed by on-chip APBs that are attached to the higher
speed AHB. The APB performs reads and writes to peripheral registers in three peripheral
clocks.
7.2.2 FAB
Some peripherals are placed on a special bus called FAB that allows faster CPU access
to those peripheral functions. A write access to FAB peripherals takes a single AHB clock
and a read access to FAB peripherals takes two AHB clocks.
7.3 Physical memory map
The physical memory map incorporates several distinct regions, as shown in Figure 3.
When an application is running, the CPU interrupt vectors are re-mapped to allow them to
reside in on-chip SRAM (IRAM).