Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 3 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
 Six enhanced timer/counters which are architecturally identical except for the
peripheral base address. Two capture inputs and two match outputs are pinned out
to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all
four match outputs, timer 4 has one match output, and timer 5 has no inputs or
outputs.
 32-bit millisecond timer driven from the RTC clock. This timer can generate
interrupts using two match registers.
 WatchDog timer clocked by the peripheral clock.
 Two single-output PWM blocks.
 Motor control PWM.
 Keyboard scanner function allows automatic scanning of an up to 8  8 key matrix.
 Up to 18 external interrupts.
 Standard ARM test/debug interface for compatibility with existing tools.
 Emulation Trace Buffer (ETB) with 2048  24 bit RAM allows trace via JTAG.
 Stop mode saves power while allowing many peripheral functions to restart CPU
activity.
 On-chip crystal oscillator.
 An on-chip PLL allows CPU operation up to the maximum CPU rate without the
requirement for a high frequency crystal. Another PLL allows operation from the
32 kHz RTC clock rather than the external crystal.
 Boundary scan for simplified board testing.
 User-accessible unique serial ID number for each chip.
 TFBGA296 package with a 15 mm  15 mm  0.7 mm body.
3. Applications
 Consumer
 Medical
 Industrial
 Network control