Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 38 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3220/30/40/50 does not support operation as a slave.
7.8.2.1 Features
• Supports slaves compatible with SPI modes 0 to 3.
• Half duplex synchronous transfers.
• DMA support for data transmit and receive.
• 1-bit to 16-bit word length.
• Choice of LSB or MSB first data transmission.
• 64  16-bit input or output FIFO.
• Bit rates up to 52 Mbit/s.
• Busy input function.
• DMA time out interrupt to allow detection of end of reception when using DMA.
• Timed interrupt to facilitate emptying the FIFO at the end of a transmission.
• SPI clock and data pins may be used as general purpose pins if the SPI is not used.
• Slave selects can be supported using GPO or GPIO pins
7.8.3 SSP serial I/O controller
The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.8.3.1 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• Maximum SPI bus data bit rate of
1
⁄
2
(Master mode) and
1
⁄
2
(Slave mode) of the input
clock rate
• DMA transfers supported by GPDMA
7.8.4 I
2
C-bus serial I/O controller
There are two I
2
C-bus interfaces in the LPC32x0 family of controllers. These I
2
C blocks
can be configured as a master, multi-master or slave supporting up to 400 kHz. The I
2
C
blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit
and receive. An interrupt signal is available from each block.