Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 5 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
5. Block diagram
Fig 1. Block diagram of LPC3220/30/40/50
ARM
9EJS
D-CACHE
32 kB
I-CACHE
32 kB
DATA
INSTRUCTION
ethernet
PHY
interface
USB
transceiver
interface
LCD
panel
interface
EXTERNAL
MEMORY
CONTROLLER
ROM
16 kB
SRAM
256 kB
USB DMA ETBSDRAM
STANDARD
UART × 4
I2C
× 2
TIMERS
× 6
WATCHDOG
TIMER
DEBUG
SYSTEM
CONTROL
HS UART
× 3
KEY
SCANNER
10-BIT
ADC/TS
UART
CONTROL
RTC
PWM
× 2
GPIO
M1M0
AHB
TO
APB
BRIDGE
AHB
TO
APB
BRIDGE
AHB
TO
APB
BRIDGE
master layer
0123456
slave port
0
1
7
6
5
3
2
= Master/Slave connection supported
by the multilayer AHB matrix
32-bit AHB matrix
APB slaves
FAB slaves
AHB slaves
APB slaves
port 3
port 4
port 0
32-bit wide
external
memory
ETB
ETM 9
VFP9
LCDETHERNET
MOTOR
CONTROL PWM
002aae397
MMU
D-SIDE
CONTROLLER
I-SIDE
CONTROLLER
DMA
CONTROLLER
ETHERNET
10/100
MAC
USB OTG
CONTROLLER
LCD
CONTROLLER
MLC
NAND
SLC
NAND
SD
CARD
SPI
× 2
I2S
× 2
SSP
× 2
INTERRUPT
CONTROL
register interfaces