Datasheet
LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 54 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
10.4 Power consumption in Run mode
Power consumption is shown in Figure 5 for WinCE applications running under typical
conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on
but not used. I
2
S-interface (channel 1), LCD, SLC NAND controller, I
2
C1-bus, SD card,
touchscreen ADC, and UART 3 are turned on. All other peripherals are turned off.
The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is
the maximum allowed HCLK frequency. For higher core frequencies, the HCLK PLL
output must be divided by 2 to obtain an HCLK frequency lower than or equal to 133 MHz
resulting in correspondingly lower power consumption by the AHB peripherals.
Conditions: T
amb
=25C; VDD_CORE = 1.2 V for core frequencies 208 MHz;
VDD_CORE = 1.35 V for core frequencies > 208 MHz; V
DD(IO)
= 1.8 V.
(1) WinCE running from SDRAM; playing wmv file at 20 frames/s, 32 kHz mono.
(2) WinCE running from SDRAM; playing mp3 file at 128 kbit/s, stereo.
(3) WinCE running from SDRAM; no application running.
Fig 5. Core current versus core frequency for WinCE applications
core frequency (MHz)
40 280200120
002aae762
80
40
120
160
I
DD(run)
(mA)
0
(1)
(2)
(3)
HCLK = 133 MHz
HCLK = 72 MHz
VDD_CORE =
1.2 V
VDD_CORE =
1.35 V