Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 55 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
10.5 ADC static characteristics
[1] Conditions: V
SSA
= 0 V (on pin VSS_AD); V
DDA(3V3)
= 3.3 V (on pin VDD_AD).
[2] The ADC is monotonic; there are no missing codes.
[3] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 6.
[4] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 6
.
[5] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 6
.
[6] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 6
.
[7] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 6
.
Table 10. ADC static characteristics
V
DDA(3V3)
=3.3V; T
amb
=25  C unless otherwise specified; ADC clock frequency 4.5 MHz.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DDA(3V3)
V
C
ia
analog input capacitance - - 1 pF
E
D
differential linearity error
[1][2][3]
- 0.5 1LSB
E
L(adj)
integral non-linearity
[1][4]
- 0.6 1LSB
E
O
offset error
[1][5]
- 1 3LSB
E
G
gain error
[1][6]
- 0.3 0.6 %
E
T
absolute error
[1][7]
- 4LSB
R
vsi
voltage source interface resistance - - 40 k