Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 60 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.3 SDR SDRAM Controller
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V,
VDD_CORE = 1.2 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual).
[3] All min or max values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC
= 3.3 V, VDD_CORE = 1.2 V.
[4] f
oper
= 1/t
CK.
[5] Applies to signals: EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0].
[6] CMD_DLY = COMMAND_DELAY bit field in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in
LPC32x0 User manual.
Table 13. EMC SDR SDRAM memory interface dynamic characteristics
C
L
=25pF, T
amb
=  40  C to +85  C, unless otherwise specified.
[1][3]
Symbol Parameter Min Typical
[2]
Max Unit
f
oper
operating frequency
[4]
104 133 MHz
t
CK
clock cycle time 7.5 9.6 - ns
t
CL
CK LOW-level width - 4.8 - ns
t
CH
CK HIGH-level width - 4.8 - ns
t
d(V)ctrl
control valid delay time
[5][6]
- (CMD_DLY  0.25) + 2.7 ns
t
h(ctrl)
control hold time
[5][6]
(CMD_DLY  0.25) + 1.2 - ns
t
d(AV)
address valid delay time
[6]
- (CMD_DLY  0.25) + 3.2 ns
t
h(A)
address hold time
[6]
(CMD_DLY  0.25) + 1.2 - ns
t
d(QV)
data output valid delay time
[6]
- (CMD_DLY  0.25) + 3.5 ns
t
h(Q)
data output hold time
[6]
(CMD_DLY  0.25) + 1.2 - ns
t
su(D)
data input set-up time - 0.6 - ns
t
h(D)
data input hold time - 0.9 - ns
t
QZ
data output high-impedance time - -  t
CK
ns
Fig 9. SDR SDRAM signal timing
002aae420
EMC_CLK
output signal (O)
input signal (I)
t
d(V)ctrl
, t
d(AV)
, t
d(QV)
t
h(ctrl)
, t
h(Q)
, t
h(A)
t
h(D)
t
su(D)
t
CK
t
CL
t
CH
t
QZ