Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 61 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.4 DDR SDRAM controller
[1] All values valid for EMC pads set to fast slew rate at 1.8 V unless otherwise specified (see SDRAMCLK_CTRL register in the LPC32x0
User manual).
[2] CMD_DLY = COMMAND_DELAY bit field in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in
LPC32x0 User manual.
[3] Applies to signals EMC_DQM[3:0], EMC_DYCS[1:0]
, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0].
[4] DQS_DELAY, see LPC32x0 User manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on
configuring this value.
[5] Test conditions for measurements: T
amb
= 40 C to +85 C; operating frequency range f
oper
= 52 MHz to 133 MHz; EMC_DQM[3:0] and
EMC_D[31:0] driving 2 inches of 50  characteristic impedance trace with 10 pF capacitive load; no external source series termination
resistors used. EMC pads set to fast slew rate at 1.8 V or 2.5 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual).
Table 14. EMC DDR SDRAM memory interface dynamic characteristics
[1]
C
L
=25pF, T
amb
=25  C, unless otherwise specified.
Symbol Parameter Conditions Min Typical Max Unit
f
oper
operating frequency - 104 133 MHz
t
CK
clock cycle time 7.5 9.6 - ns
t
CL
CK LOW-level width - 0.5  t
CK
-ns
t
CH
CK HIGH-level width - 0.5  t
CK
-ns
t
d(V)ctrl
control valid delay time
[2][3]
- (CMD_DLY  0.25) + 1.5 - ns
t
h(ctrl)
control hold time
[2][3]
- (CMD_DLY  0.25)  1.5 - ns
t
d(AV)
address valid delay time
[2]
- (CMD_DLY  0.25) + 1.5 - ns
t
h(A)
address hold time
[2]
- (CMD_DLY  0.25)  1.5 - ns
t
su(Q)
data output set-up time EMC_D[31:0]
and
EMC_DQM[3:0]
to
EMC_DQS[1:0]
out
[5]
0.08
 t
CK
0.15  t
CK
0.25
 t
CK
ns
t
h(Q)
data output hold time EMC_D[31:0]
and
EMC_DQM[3:0]
to
EMC_DQS[1:0]
out
[5]
0.25
 t
CK
0.35  t
CK
0.42
 t
CK
ns
t
DQSH
DQS HIGH time for WRITE
command
-0.5  t
CK
-ns
t
DQSL
DQS LOW time for WRITE
command
-0.5  t
CK
-ns
t
DQSS
WRITE command to first DQS latching
transition time
for DQS out - t
CK
+ 0.7 - ns
t
DSS
DQS falling edge to CK set-up time for DQS in - 0.5  t
CK
-ns
t
DSH
DQS falling edge hold time from CK for DQS in - 0.5  t
CK
-ns
t
d(DQS)
DQS delay time for DQS in
[4]
-DQS_DELAY -ns
t
su(D)
data input set-up time - 0.3 - ns
t
h(D)
data input hold time - 0.5 - ns