Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 62 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Fig 10. DDR control timing parameters
EMC_CLK
EMC control
and address
signals
002aae436
t
CK
t
CH
t
CL
t
d(AV);
t
d(V)ctrl
t
h(A);
t
h(ctl)
valid
Fig 11. DDR write timing parameters
command
EMC_D[31:0],
EMC_DQM[3:0]
t
DQSL
t
DQSH
t
DQSS
t
h(Q)
EMC_DQS[1:0]
EMC_CLK
002aae437
WRITE
t
su(Q)
t
DSH
t
DSS
(1) The delay of the EMC_DQS[1:0] signal is determined by the DQS_DELAY settings. See LPC32x0 User manual, External
Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value.
Fig 12. DDR read timing parameters
EMC_CLK
command
EMC_D[31:0]
t
su(D)
EMC_DQS[1:0]
002aae438
t
h(D)
READ
delayed EMC_DQS[1:0]
(1)
t
d(DQS)