Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 64 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.7 MLC NAND flash memory controller
[1] T
HCLK
= 1/HCLK
[2] CEA
D
= bit field TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24]
[3] W
L
= bit field WR_LOW[3:0] in register MLC_TIME_REG[3:0]
[4] W
H
= bit field WR_HIGH[3:0] in register MLC_TIME_REG[7:4]
[5] R
L
= bit field RD_LOW[3:0] in register MLC_TIME_REG[11:8]
[6] R
H
= bit field RD_HIGH [3:0] in register MLC_TIME_REG[15:12]
[7] R
HZ
= bit field NAND_TA[2:0] in register MLC_TIME_REG[18:16]
[8] B
D
= bit field BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19]
Fig 14. SD card pin interface timing
002aae441
MS_SCLK
MS_DIO[3:0](O)
MS_DIO[3:0] (I)
t
d(QV)
t
h(D)
t
su(D)
T
cy(clk)
t
h(Q)
MS_BS (O)
MS_BS (I)
Table 17. Dynamic characteristics of the MLC NAND flash memory controller
T
amb
=  40  C to +85  C.
Symbol Parameter Min Typ Max Unit
t
CELREL
CE LOW to RE LOW time
[1][2]
-T
HCLK
 CEA
D
-ns
t
RC
RE cycle time
[1][5][6]
-T
HCLK
 (R
L
+ 1) + T
HCLK
 (R
H
 R
L
)- ns
t
REH
RE HIGH hold time
[1][5][6]
-T
HCLK
 (R
H
 R
L
)-ns
t
RHZ
RE HIGH to output high-impedance time
[1][5][7]
-T
HCLK
 (R
H
 R
L
) + T
HCLK
 R
HZ
-ns
t
RP
RE pulse width
[1][5]
-T
HCLK
 (R
L
+ 1) - ns
t
REHRBL
RE HIGH to R/B LOW time
[1][8]
-T
HCLK
 B
D
-ns
t
WB
WE HIGH to R/B LOW time
[1][8]
-T
HCLK
 B
D
-ns
t
WC
WE cycle time
[1][3][4]
-T
HCLK
 (W
L
+ 1) + T
HCLK
 (W
H
 W
L
)- ns
t
WH
WE HIGH hold time
[1][3][4]
-T
HCLK
 (W
H
 W
L
)-ns
t
WP
WE pulse width
[1][3]
-T
HCLK
 (W
L
+ 1) - ns