Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 66 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
t
CEA
CE access time read
[1][2][4][6][8]
-T
HCLK
 (Rsu + Rw) - ns
write - T
HCLK
 (Wsu + Ww) - ns
t
CS
CE set-up time read
[1][2][4][6][8]
-T
HCLK
 (Rsu + Rw) - ns
write - T
HCLK
 (Wsu + Ww) - ns
t
CH
CE hold time read
[1][3]
-T
HCLK
 Rh - ns
write - T
HCLK
 Wh - ns
t
CLS
CLE set-up time read
[1][2][4][6][8]
-T
HCLK
 (Rsu + Rw) - ns
write - T
HCLK
 (Wsu + Ww) - ns
t
CLH
CLE hold time read
[1][3]
-T
HCLK
 Rh - ns
write - T
HCLK
 Wh - ns
t
CLR
CLE to RE delay time read
[1][2][6]
-T
HCLK
 Rsu - ns
write - T
HCLK
 Wsu - ns
t
DH
data hold time output from
NAND
controller; read
[1][3][7]
-T
HCLK
 Rh - ns
output from
NAND
controller;
write
-T
HCLK
 Wh - ns
t
DS
data set-up time output from
NAND
controller; read
[1][2][4][6][8]
-T
HCLK
 (Rsu + Rw) - ns
output from
NAND
controller;
write
-T
HCLK
 (Wsu + Ww) -
t
IR
output high-impedance to RE
LOW time
read
[1][2][6]
-T
HCLK
 Rsu - ns
write - T
HCLK
 Wsu - ns
t
RC
RE cycle time read
[1][2]
-T
HCLK
 (Rsu + Rw + Rh) - ns
t
REA
RE access time read
[1][4]
-T
HCLK
 Rw - ns
t
REH
RE high hold time read
[1][2][3]
-T
HCLK
 (Rsu + Rh) - ns
t
RHOH
RE HIGH to output hold time input hold for
flash
controller; read
-0 --
input hold for
flash
controller;
write
-0 --
t
RHZ
RE HIGH to output
high-impedance time
read
[1]
-T
HCLK
 Rh - ns
t
RP
RE pulse width read
[1][4]
-T
HCLK
 Rw - ns
t
RR
ready to RE LOW time read
[1][2][3]
-T
HCLK
 Rsu - ns
t
WB
WE HIGH to R/B LOW time write
[1][7][9]
-(T
HCLK
 Wh) + (2  T
HCLK
 Wb)
-ns
t
WC
WE cycle time write
[1][6][7][8]
-T
HCLK
 (Wsu + Ww + Wh) - ns
Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued
T
amb
=  40  C to +85  C.
Symbol Parameter Conditions Min Typ Max Unit