Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 69 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.9 SPI and SSP Controller
11.9.1 SPI
[1] T
HCLK
= period time of SPI IP block input clock (HCLK)
Fig 19. MLC NAND flash memory status timing
t
CS
t
CH
t
CEA
70 h
t
DS
t
DH
status
t
RHOH
t
CLS
t
CLH
command data
t
CLR
t
COH
t
REA
t
IR
FLASH_IO[7:0]
t
WHR
t
WP
t
RHZ
FLASH_CLE
FLASH_WR
FLASH_CE
FLASH_RD
002aae446
Table 19. Dynamic characteristics of SPI pins on SPI master controller
T
amb
=  40  C to +85  C.
Symbol Parameter Min Typ Max Unit
Common to SPI1 and SPI2
T
SPICYC
SPI cycle time
[1]
2  T
HCLK
- 256  T
HCLK
ns
SPI1
t
SPIDSU
SPI data set-up time - 6 - ns
t
SPIDH
SPI data hold time - 0 - ns
t
SPIDV
SPI enable to output data valid time - 2 - ns
t
SPIOH
SPI output data hold time - 0 - ns
SPI2
t
SPIDSU
SPI data set-up time - 10 - ns
t
SPIDH
SPI data hold time - 0 - ns
t
SPIDV
SPI enable to output data valid time - 2 - ns
t
SPIOH
SPI output data hold time - 0 - ns