Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 70 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.9.2 Timing diagrams for SPI and SSP (in SPI mode)
Fig 20. SPI master timing (CPHA = 0)
Fig 21. SPI master timing (CPHA = 1)
002aae457
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
DATA VALID DATA VALID
t
SPIOH
DATA VALID
DATA VALID
t
SPIQV
SPI1/2_CLK or
SCK0/1 (CPOL = 0)
SPI1/2_CLK or
SCK0/1 (CPOL = 1)
SPI1/2_DATAIO or
MOSI0/1
SPI1/2_DATAIN or
MISO0/1
002aae454
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID DATA VALID
t
SPIOH
DATA VALID
DATA VALID
SPI1/2_CLK or
SCK0/1 (CPOL = 0)
SPI1/2_CLK or
SCK0/1 (CPOL = 1)
SPI1/2_DATAIO or
MOSI0/1
SPI1/2_DATAIN or
MISO0/1