Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 71 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
12. Application information
12.1 Connecting the JTAG_NTRST pin
To ensure that pin JTAG_NTRST is LOW at POR, use one the following board design
options:
• Tie JTAG_NTRST LOW. In this case, you will not be able to use the JTAG port in a
production design. Tying JTAG_NTRST LOW does not affect normal operation (code
execution) of the part but does prevent JTAG access.
• Implement recommended circuit shown in Figure 24.
Fig 22. SPI slave timing (CPHA = 0)
Fig 23. SPI slave timing (CPHA = 1)
002aae458
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID DATA VALID
t
SPIOH
DATA VALID
DATA VALID
SPI1/2_CLK or
SCK0/1 (CPOL = 0)
SPI1/2_CLK or
SCK0/1 (CPOL = 1)
SPI1/2_DATAIO or
MOSI0/1
SPI1/2_DATAIN or
MISO0/1
002aae459
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID DATA VALID
t
SPIOH
DATA VALID
DATA VALID
SPI1/2_CLK or
SCK0/1 (CPOL = 0)
SPI1/2_CLK or
SCK0/1 (CPOL = 1)
SPI1/2_DATAIO or
MOSI0/1
SPI1/2_DATAIN or
MISO0/1