Datasheet

LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.1 — 24 June 2014 76 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
16. Revision history
Table 21. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC3220_30_40_50 v.2.1 20140624 Product data sheet CIN 201110012I LPC3220_30_40_50 v.2
Modifications: Section 12.1 “
Connecting the JTAG_NTRST pin” added.
LPC3220_30_40_50 v.2 20111020 Product data sheet - LPC3220_30_40_50 v.1
Modifications:
• Corrected pin functions for pin T14 (ADIN1/TS_XM) and pin U15 (ADIN0/TS_YM) in
Table 3 and Table 4.
• Power domain for pin PLL397_LOOP corrected in Table 4.
• Power supply domain for pins SYSX_IN and SYSX_OUT pins corrected in Table 4.
• Power supply domain for pin VDD_OSC corrected in Table 4.
• Description of DEBUG pin updated in Table 4.
• Added Table 6 “Supply domains”.
• Changed V
ESD
to 2500 V (HBM) and 1000 V (CDM) in Table 7.
• Power consumption for HCLK, USB, and ADC added in Table 8.
• Parameter I
DD(RTC)
updated in Table 8.
• Parameter V
DD(EMC)
table notes updated in Table 8.
• Input current for bus keeper inputs added in Table 8.
• Added power consumption data (Table 8, Table 9, and Figure 5).
• Static memory controller: added t
su(DQ)
value in Table 12.
• DDR SDRAM controller: updated t
DQSS
value in Table 14.
• Minimum and maximum characterization data added for parameters t
su(Q)
and t
h(Q)
over
temperature range 40 C to +85 C (see Table 14).
• DDR SDRAM characteristics extended to maximum operating frequency f
oper
= 133 MHz
(see Table 14).
• Parameters t
WB
, t
WHR
, and t
REHRBL
updated in Table 18.
• Changed data sheet status to Product data sheet.
• Parts LPC3220FET296/01, LPC3230FET296/01, LPC3240FET296/01,
LPC3250FET296/01 added.
LPC3220_30_40_50 v.1 20090206 Preliminary data sheet - -