Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 120 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
11.14 SPIFI
11.15 SGPIO timing
The following considerations apply to SGPIO timing:
• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To
guarantee that no samples are missed, all input signals should have a duration of at
least one SGPIO_CLOCK cycle plus the set-up and hold times.
• When an external clock input is used to generate output data, synchronization causes
a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one
output every two SGPIO_CLOCK cycles.
• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling
several inputs. This may cause inputs with very similar timings to be sampled with a
difference of one SGPIO_CLOCK cycle.
Table 27. Dynamic characteristics: SPIFI
T
amb
=  40  C to 105  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V. C
L
= 10 pF.
Simulated values.
Symbol Parameter Min Max Unit
T
cy(clk)
clock cycle time 9.6 - ns
t
DS
data set-up time 3.4 - ns
t
DH
data hold time 0 - ns
t
v(Q)
data output valid time - 3.2 ns
t
h(Q)
data output hold time 0.2 - ns
Fig 32. SPIFI timing (Mode 0)
SPIFI_SCK
SPIFI data out
SPIFI data in
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
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