Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 130 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
11.19 SD/MMC
11.20 LCD
Table 35. Dynamic characteristics: SD/MMC
T
amb
=  40  C to 85  C, 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V, C
L
= 20 pF. Simulated
values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC43xx
user manual UM10430).
Symbol Parameter Conditions Min Max Unit
f
clk
clock frequency on pin SD_CLK; data transfer mode 52 MHz
t
su(D)
data input set-up time on pins SD_DATn as inputs 6 - ns
on pins SD_CMD as inputs 7 - ns
t
h(D)
data input hold time on pins SD_DATn as inputs -1 - ns
on pins SD_CMD as inputs 1ns
t
d(QV)
data output valid delay
time
on pins SD_DATn as outputs - 17 ns
on pins SD_CMD as outputs - 18 ns
t
h(Q)
data output hold time on pins SD_DATn as outputs 4 - ns
on pins SD_CMD as outputs 4 - ns
Fig 39. SD/MMC timing
002aag204
SD_CLK
SD_DATn (O)
SD_DATn (I)
t
d(QV)
t
h(D)
t
su(D)
T
cy(clk)
t
h(Q)
SD_CMD (O)
SD_CMD (I)
Table 36. Dynamic characteristics: LCD
T
amb
=  40  C to 105  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V; C
L
= 20 pF.
Simulated values.
Symbol Parameter Conditions Min Typ Max Unit
f
clk
clock frequency on pin LCD_DCLK - 50 - MHz
t
d(QV)
data output valid
delay time
- - 17 ns
t
h(Q)
data output hold time 8.5 - - ns