Datasheet
LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 153 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
Modifications: • SD/MMC timing data updated. See Table 35 “Dynamic characteristics: SD/MMC”.
• IEEE standard 802.3 compliance added to Section 11.18. Covers Ethernet dynamic
characteristics of ENET_MDIO and ENET_MDC signals.
• SSP master mode timing diagram updated with SSEL timing parameters. See Figure
30 “SSP in SPI mode and SPI master timing”.
• Parameters t
lead
, t
lag
, and t
d
added in Table 25 “Dynamic characteristics: SSP pins in
SPI mode”.
• Parameter t
CSLWEL
with condition PB = 1 corrected: (WAITWEN + 1) T
cy(clk)
added.
See Table 29 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Parameter t
CSLBLSL
with condition PB = 0 corrected: (WAITWEN + 1) T
cy(clk)
added.
See Table 29 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Removed restriction on C_CAN bus usage. See CAN.1 errata in Ref. 2.
• General-purpose OTP size corrected.
LPC435X_3X_2X_1X v.3 20121206 Preliminary data sheet - LPC4357_53_37_33 v.2.1
Modifications:
• TFBGA180 packages removed.
• Part LPC432x and LPC431x added.
• SCT dither engine added and SCT bi-directional event enable features added.
• Figure 10 “Dual-core debug configuration” added.
• T = 105 °C data added in Figure 20 to Figure 23.
• Change symbol names and parameter names in Table 21.
• Parameter I
LH
updated for condition V
I
= 5 V and T
amb
= 25 °C/105 °C in Table 11.
• Power consumption data added in Section 10.1.
• SPIFI dynamic characteristics added in Section 11.16.
• IRC accuracy corrected to 2 % for T
amb
= -40 °C to 0 °C and T
amb
= 85 °C to 105 °C.
• Pull-up and Pull-down current data (Figure 24 and Figure 25) updated with data for
T
amb
= 105 °C.
• SPIFI maximum data rate changed to 52 MB per second.
• Recommendation for V
BAT
use added: The recommended operating condition for the
battery supply is V
DD(REG)(3V3)
> V
BAT
+ 0.2 V.
• Table 14 “Band gap characteristics” added.
• Section 7.23.9 “Power Management Controller (PMC)” added.
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC
is connected to ADC0 and ADC1. See Table 3.
• OTP memory size changed to 64 bit.
• Use of C_CAN peripheral restricted in Section 2.
• ADC channels limited to a total of 8 channels shared between ADC0 and ADC1.
LPC4357_53_37_33 v.2.1 20120904 Preliminary data sheet - LPC4357_53_37_33 v.2
Modifications:
• SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin
P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• SWD removed for ARM Cortex-M0.
• BOD de-assertion levels added in Table 13.
• Peripheral power consumption data added in Table 12.
• Minimum value for all supply voltages changed to -0.5 V in Table 7.
Table 45. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes