Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 57 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
Debug pins
DBGEN L4 A6 41 28
[2]
I I JTAG interface control signal. Also used for boundary scan. To
use the part in functional mode, connect this pin in one of the
following ways:
• Leave DBGEN open. The DBGEN pin is pulled up
internally by a 50 kΩ resistor.
• Tie DBGEN to VDDIO.
• Pull DBGEN up to VDDIO with an external pull-up
resistor.
TCK/SWDCLK J5 H2 38 27
[2]
I; F I Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.
TRST
M4 B4 42 29
[2]
I; PU I Test Reset for JTAG interface.
TMS/SWDIO K6 C4 44 30
[2]
I; PU I Test Mode Select for JTAG interface (default) or SW debug
data input/output.
TDO/SWO K5 H3 46 31
[2]
O O Test Data Out for JTAG interface (default) or SW trace output.
TDI J4 G3 35 26
[2]
I; PU I Test Data In for JTAG interface.
USB0 pins
USB0_DP F2 E1 26 18
[6]
- I/O USB0 bidirectional D+ line. Do not add an external series
resistor.
USB0_DM G2 E2 28 20
[6]
- I/O USB0 bidirectional D line. Do not add an external series
resistor.
USB0_VBUS F1 E3 29 21
[6]
[7]
- I/O VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 64 k (typical)  16 k.
USB0_ID H2 F1 30 22
[8]
- I Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this
pin has an internal pull-up resistor.
USB0_RREF H1 F3 32 24
[8]
- 12.0 k (accuracy 1 %) on-board resistor to ground for current
reference.
USB1 pins
USB1_DP F12 E9 129 89
[9]
- I/O USB1 bidirectional D+ line. Add an external series resistor of
33  +/- 2 %.
USB1_DM G12 E10 130 90
[9]
- I/O USB1 bidirectional D line. Add an external series resistor of
33  +/- 2 %.
I
2
C-bus pins
I2C0_SCL L15 D6 132 92
[10]
I; F I/O I
2
C clock input/output. Open-drain output (for I
2
C-bus
compliance).
I2C0_SDA L16 E6 133 93
[10]
I; F I/O I
2
C data input/output. Open-drain output (for I
2
C-bus
compliance).
Reset and wake-up pins
RESET
D9 B6 185 128
[11]
I; IA I External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. This
pin does not have an internal pull-up.
Table 3. Pin description
…continued
Pin name
LBGA256 TFBGA100 LQFP208 LQFP144 Reset state [1] Type
Description