Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 62 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
7.5 AHB multilayer matrix
7.6 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
Fig 6. AHB multilayer matrix master and slave connections
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
DMA ETHERNET USB1USB0 LCD
SD/
MMC
EXTERNAL
MEMORY
CONTROLLER
APB, RTC
DOMAIN
PERIPHERALS
HIGH-SPEED PHY
System
bus
I-
code
bus
D-
code
bus
masters
01
AHB MULTILAYER MATRIX
= master-slave connection
SPIFI
AHB PERIPHERALS
REGISTER
INTERFACES
002aah080
32 kB AHB SRAM
16 kB AHB SRAM
16 kB AHB SRAM
slaves
64 kB ROM
32 kB LOCAL SRAM
40 kB LOCAL SRAM
256/512 kB FLASH A
256/512 kB FLASH B
16 kB EEPROM