Datasheet

Product data sheet Rev. 4 — 19 August 2014 63 of 158

NXP Semiconductors

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.6.1 Features

• ARM Cortex-M4 core:

– Controls system exceptions and peripheral interrupts

– Support for up to 53 vectored interrupts

– Eight programmable interrupt priority levels with hardware priority level masking

– Relocatable vector table

– Non-Maskable Interrupt (NMI)

– Software interrupt generation

• ARM Cortex-M0 core:

– Support for up to 32 interrupts

– Four programmable interrupt priority levels with hardware priority level masking

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.7 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

Remark: The SysTick is not included in the ARM Cortex-M0 core implementation.

7.8 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event

router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,

Deep-sleep, Power-down, and Deep power-down modes. Individual events can be

configured as edge or level sensitive and can be enabled or disabled in the event router.

The event router can be battery powered.

The following events if enabled in the event router can create a wake-up signal from

sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC (32 kHz oscillator running)

The following events if enabled in the event router can create a wake-up signal from sleep

mode only and/or create an interrupt:

• WWDT, BOD interrupts

• C_CAN0/1 and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCT and timer0/1/3)