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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 32-Bit Dual-Core 204 MHz I/O number 83
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LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 64 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in
the NVIC.
7.9 Global Input Multiplexer Array (GIMA)
The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers,
event router, or the ADCs.
7.9.1 Features
• Single selection of a source.
• Signal inversion.
• Can capture a pulse if the input event source is faster than the target clock.
• Synchronization of input event and target clock.
• Single-cycle pulse generation for target.
7.10 On-chip static RAM
The LPC435x/3x/2x/1x support up to 136 kB SRAM with separate bus master access for
higher throughput and individual power control for low power operation.
7.11 On-chip flash memory
The LPC435x/3x/2x/1x contain up to 1 MB of dual-bank flash program memory. With
dual-bank flash memory, the user code can write or erase one flash bank while reading
the other flash bank without interruption. A two-port flash accelerator maximizes the flash
performance.
In-System Programming (ISP) and In-Application Programming (IAP) routines for
programming the flash memory are provided in the Boot ROM.
7.12 EEPROM
The LPC435x/3x/2x/1x contain 16 kB of on-chip byte-erasable and byte-programmable
EEPROM memory.
The EEPROM memory is divided into 128 pages. The user can access pages 1 through
127. Page 128 is protected.
7.13 Boot ROM
The internal ROM memory is used to store the boot code of the LPC435x/3x/2x/1x. After a
reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• The ROM memory size is 64 kB.
• Supports booting from external static memory such as NOR flash, SPI flash, quad SPI
flash, USB0, and USB1.
• Includes API for OTP programming.
• Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.