Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 66 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
7.14 Memory mapping
The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the
Cortex-M0 processors and all SRAM, flash, and EEPROM memory is shared between
both processors. Each processor uses its own ARM private bus memory map for the
NVIC and other system functions.
USB1 LOW HIGH HIGH LOW Boot from USB1.
SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)
[1]
.
USART3 HIGH LOW LOW LOW Enter ISP mode using USART3 pins P2_3 and
P2_4.
Table 5. Boot mode when OPT BOOT_SRC bits are zero
Boot mode Pins Description
P2_9 P2_8 P1_2 P1_1