Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 72 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Simple sequences of commands handle erasing and
programming.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.18.2.1 Features
Interfaces to serial flash memory in the main memory map.
Supports classic and 4-bit bidirectional serial protocols.
Half-duplex protocol compatible with various vendors and devices.
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per
second.
Supports DMA access.
7.18.3 SD/MMC card interface
The SD/MMC card interface supports the following modes to control:
Secure Digital memory (SD version 3.0)
Secure Digital I/O (SDIO version 2.0)
Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
MultiMedia Cards (MMC version 4.4)
7.18.4 External Memory Controller (EMC)
Remark: The EMC is available on all LPC435x/3x/2x/1x parts. The following memory bus
widths are supported:
LBGA256 packages: 32 bit
TFBGA100 packages: 8 bit
LQFP208 packages: 16 bit
LQFP144 packages: 16 bit
The LPC435x/3x/2x/1x EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it
can be used as an interface with off-chip memory-mapped devices and peripherals.
Table 6. EMC pinout for different packages
Function LBGA256 TFBGA100 LQFP208 LQFP144
A EMC_A[23:0] EMC_A[13:0] EMC_A[23:0] EMC_A[15:0]
D EMC_D[31:0] EMC_D[7:0] EMC_D[15:0] EMC_D[15:0]
BLS
EMC_BLS[3:0] EMC_BLS0 EMC_BLS[1:0] EMC_BLS[1:0]
CS EMC_CS[3:0] EMC_CS0 EMC_CS[3:0] EMC_CS[1:0]