Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 78 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• DMA transfers supported by GPDMA
7.19.5 I
2
C-bus interface
Remark: The LPC435x/3x/2x/1x each contain two I
2
C-bus interfaces.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and
can be controlled by more than one bus master connected to it.
7.19.5.1 Features
• I
2
C0 is a standard I
2
C compliant bus interface with open-drain pins. I
2
C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I
2
C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus can be used for test and diagnostic purposes.
• All I
2
C-bus controllers support multiple address recognition and a bus monitor mode.
7.19.6 I
2
S interface
Remark: The LPC435x/3x/2x/1x each contain two I
2
S-bus interfaces.
The I
2
S-bus provides a standard communication interface for digital audio applications.
The I
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I
2
S-bus connection has one master, which is
always the master, and one slave. The I
2
S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.