Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 8 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
6. Pinning information
6.1 Pinning
6.2 Pin description
On the LPC435x/3x/2x/1x, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin can support up to eight different
digital functions, including General Purpose I/O (GPIO), selectable through the System
Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port
assigned to it.
The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and
ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel
0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel
Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA100 package
002aah177
LPC435x/3xFET256
Transparent top view
T
R
P
N
M
L
J
G
K
H
F
E
D
C
B
A
2 4 6 8 10 12
13
14
15
16
1357911
ball A1
index area
002aah179
LPC433x/2x/1xFET100
Transparent top view
J
G
K
H
F
E
D
C
B
A
24681013579
ball A1
index area
Fig 4. Pin configuration LQFP208 package Fig 5. Pin configuration LQFP144 package
LPC4357/53FBD208
104
1
52
156 105
53
157
208
002aah180
LPC433x/2x/1xFBD144
72
1
36
108
73
37
109
144
002aah181