Datasheet

Product data sheet Rev. 4 — 19 August 2014 83 of 158

NXP Semiconductors

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

• Alarm interrupt can be generated for a specific date/time.

7.22.1.2 Event monitor/recorder

The event monitor/recorder allows recording and creating a time stamp of events related

to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the

event monitor/recorder stores records of such events. The event recorder can be

The event monitor/recorder can monitor the integrity of the device and record any

tampering events.

Features

• Supports three digital event inputs in the VBAT power domain.

• An event is defined as a level change at the digital event inputs.

• For each event channel, two timestamps mark the first and the last occurrence of an

event. Each channel also has a dedicated counter tracking the total number of events.

Timestamp values are taken from the RTC.

• Runs in VBAT power domain, independent of system power supply. The

event/recorder/monitor can therefore operate in Deep power-down mode.

• Low power consumption.

• Interrupt available if system is running.

• A qualified event can be used as a wake-up trigger.

• State of event interrupts accessible by software through GPIO.

7.22.2 Alarm timer

The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt if enabled.

The alarm timer is part of the RTC power domain and can be battery powered.

7.23 System control

7.23.1 Configuration registers (CREG)

The following settings are controlled in the configuration register block:

• BOD trip settings

• Oscillator output

• DMA-to-peripheral muxing

• Ethernet mode

• Memory mapping

• Timer/USART inputs

• Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.