Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 110 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.8 I
2
S-bus interface
[1] Clock to the I
2
S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I
2
S-bus interface
PCLK = BASE_APB1_CLK / 12. I
2
S clock cycle time T
cy(clk)
= 79.2 ns; corresponds to the SCK signal in the
I
2
S-bus specification.
Fig 27. I
2
C-bus pins clock timing
002aaf425
t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
70 %
30 %
70 %
30 %
t
HD;DAT
SCL
1 / f
SCL
70 %
30 %
70 %
30 %
t
VD;DAT
t
HIGH
t
LOW
t
SU;DAT
Table 20. Dynamic characteristics: I
2
S-bus interface pins
T
amb
=  40  C to +85  C ; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V; C
L
= 20 pF.
Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
Symbol Parameter Conditions Min Typ Max Unit
common to input and output
t
r
rise time - 4 - ns
t
f
fall time - 4 - ns
t
WH
pulse width HIGH on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
36 - - ns
t
WL
pulse width LOW on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
36 - - ns
output
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[1]
-4.4-ns
on pin I2Sx_TX_WS - 4.3 - ns
input
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[1]
-0-ns
on pin I2Sx_RX_WS 0.20 ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[1]
-3.7-ns
on pin I2Sx_RX_WS - 3.9 - ns