Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 113 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] T
cy(clk)
= 12  T
cy(PCLK)
.
t
d
delay time continuous transfer mode
SPI mode; CPOL = 0;
CPHA = 0
- 0.5 T
cy(clk)
--
SPI mode; CPOL = 0;
CPHA = 1
-n/a--
SPI mode; CPOL = 1;
CPHA = 0
- 0.5 T
cy(clk)
--
SPI mode; CPOL = 1;
CPHA = 1
-n/a--
synchronous serial
frame mode
-T
cy(clk)
--
microwire frame format - n/a - -
SSP slave
T
cy(PCLK)
PCLK cycle time 10 ns
T
cy(clk)
clock cycle time
[2]
120 - - ns
t
DS
data set-up time in SPI mode - 10.5 - ns
t
DH
data hold time in SPI mode - 1 - ns
t
v(Q)
data output valid
time
in SPI mode - 4.0 - ns
t
h(Q)
data output hold
time
in SPI mode - 0.2 - ns
Table 22. Dynamic characteristics: SSP pins in SPI mode
T
amb
=  40  C to +85  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V; C
L
= 20 pF. Simulated values.
Symbol Parameter Conditions Min Typ Max Unit