Datasheet
LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 115 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.12 SSP/SPI timing diagrams
Fig 30. SSP master mode timing (SPI mode)
SCK (CPOL = 0)
MOSI (CPHA = 1)
SSEL
MISO (CPHA = 1)
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID (LSB) DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID (LSB)
DATA VALID
MOSI (CPHA = 0)
MISO (CPHA = 0)
t
DS
t
lead
t
lag
t
d
t
DH
DATA VALID (MSB) DATA VALID (MSB)DATA VALID
DATA VALID (LSB)
DATA VALID (LSB)
t
h(Q)
DATA VALID (MSB)
DATA VALID
t
v(Q)
aaa-013462
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
IDLE
DATA VALID (MSB)