Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 116 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.13 SGPIO timing
The following considerations apply to SGPIO timing:
• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To
guarantee that no samples are missed, all input signals should have a duration of at
least one SGPIO_CLOCK cycle plus the set-up and hold times.
• When an external clock input is used to generate output data, synchronization causes
a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one
output every two SGPIO_CLOCK cycles.
• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling
several inputs. This may cause inputs with very similar timings to be sampled with a
difference of one SGPIO_CLOCK cycle.
Fig 31. SSP slave mode timing (SPI mode)
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
CPHA = 1
CPHA = 0
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