Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 118 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.14 External memory interface
Table 25. Dynamic characteristics: Static asynchronous external memory interface
C
L
= 22 pF for EMC_Dn C
L
= 20 pF for all others; T
amb
=  40  C to 85  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V;
2.7 V  V
DD(IO)
 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a
normal read operation, the EMC changes the address while CS is asserted resulting in multiple memory accesses.
Symbol Parameter
[1]
Conditions Min Typ Max Unit
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
3.1 - 1.6 ns
t
CSLOEL
CS LOW to OE LOW time
[2]
0.6 + T
cy(clk)

WAITOEN
- 1.3 + T
cy(clk)

WAITOEN
ns
t
CSLBLSL
CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns
t
OELOEH
OE LOW to OE HIGH time
[2]
0.6 +
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
- 0.4 +
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
ns
t
am
memory access time - - 16 +
(WAITRD 
WAITOEN +1) 
T
cy(clk)
ns
t
h(D)
data input hold time 16 - - ns
t
CSHBLSH
CS HIGH to BLS HIGH time PB = 1 0.4 - 1.9 ns
t
CSHOEH
CS HIGH to OE HIGH time 0.4 - 1.4 ns
t
OEHANV
OE HIGH to address invalid PB = 1 2.0 - 2.6 ns
t
CSHEOR
CS HIGH to end of read
time
[3]
2.0 - 0 ns
t
CSLSOR
CS LOW to start of read
time
[4]
0- 1.8ns
Write cycle parameters
t
CSLAV
CS LOW to address valid
time
3.1 - 1.6 ns
t
CSLDV
CS LOW to data valid time 3.1 - 1.5 ns
t
CSLWEL
CS LOW to WE LOW time PB = 1 1.5 +
(WAITWEN + 1)
 T
cy(clk)
- 0.2 +
(WAITWEN + 1)
 T
cy(clk)
ns
t
CSLBLSL
CS LOW to BLS LOW time PB = 1 0.7 - 1.8 ns
t
WELWEH
WE LOW to WE HIGH time PB = 1
[2]
0.6 +
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
- 0.4 +
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
ns
t
WEHDNV
WE HIGH to data invalid
time
PB = 1
[2]
0.9 + T
cy(clk)
- 2.3 + T
cy(clk)
ns
t
WEHEOW
WE HIGH to end of write
time
PB = 1
[2]
[5]
0.4 + T
cy(clk)
- 0.3 + T
cy(clk)
ns
t
CSLBLSL
CS LOW to BLS LOW PB = 0 0.7 +
(WAITWEN + 1)
 T
cy(clk)
- 1.8 +
(WAITWEN + 1)
 T
cy(clk)
ns