Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 119 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Parameters specified for 40 % of V
DD(IO)
for rising edges and 60 % of V
DD(IO)
for falling edges.
[2] T
cy(clk)
= 1/CCLK (see LPC43xx User manual).
[3] End Of Read (EOR): longest of t
CSHOEH
, t
OEHANV
, t
CSHBLSH
.
[4] Start Of Read (SOR): longest of t
CSLAV
, t
CSLOEL
, t
CSLBLSL
.
[5] End Of Write (EOW): earliest of address not valid or EMC_BLSn
HIGH.
t
BLSLBLSH
BLS LOW to BLS HIGH time PB = 0
[2]
0.9 +
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
- 0.1 +
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
ns
t
BLSHEOW
BLS HIGH to end of write
time
PB = 0
[2]
[5]
1.9 + T
cy(clk)
- 0.5 + T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data invalid
time
PB = 0
[1]
[2
]
2.5 + T
cy(clk)
- 1.4 + T
cy(clk)
ns
t
CSHEOW
CS HIGH to end of write
time
[5]
2.0 - 0 ns
t
BLSHDNV
BLS HIGH to data invalid
time
PB = 1 2.5 - 1.4 ns
t
WEHANV
WE HIGH to address invalid
time
PB = 1 0.9 + T
cy(clk)
- 2.4 + T
cy(clk)
ns
Table 25. Dynamic characteristics: Static asynchronous external memory interface
…continued
C
L
= 22 pF for EMC_Dn C
L
= 20 pF for all others; T
amb
=  40  C to 85  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V;
2.7 V  V
DD(IO)
 3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a
normal read operation, the EMC changes the address while CS is asserted resulting in multiple memory accesses.
Symbol Parameter
[1]
Conditions Min Typ Max Unit
Fig 33. External static memory read/write access (PB = 0)
t
CSLDV
t
CSLBLSL
t
CSHEOW
t
BLSHEOW
t
CSLAV
EOR
SOR
EOW
EMC_An
EMC_CSn
EMC_OE
EMC_BLSn
EMC_WE
EMC_Dn
002aag699
t
CSHOEH
t
OEHANV
t
CSHEOR
t
am
t
CSLSOR
t
OELOEH
t
CSLOEL
t
CSLAV
t
h(D)
t
BLSLBLSH
t
BLSHDNV