Datasheet
LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 121 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Program the EMC_CLKn delay values in the EMCDELAYCLK register (see the LPC43xx User manual).
The delay values must be the same for all SDRAM clocks EMC_CLKn: CLK0_DELAY = CLK1_DELAY =
CLK2_DELAY = CLK3_DELAY.
Table 26. Dynamic characteristics: Dynamic external memory interface
Simulated data over temperature and process range; C
L
= 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE,
EMC_An; C
L
= 9 pF for EMC_Dn; C
L
= 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; T
amb
=
40
C to 85
C;
2.2 V
V
DD(REG)(3V3)
3.6 V; V
DD(IO)
=3.3 V
10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY
= CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.
Symbol Parameter Min Typ Max Unit
T
cy(clk)
clock cycle time 8.4 - - ns
Common to read and write cycles
t
d(DYCSV)
DYCS delay time - 3.1 + 0.5 T
cy(clk)
5.1 + 0.5 T
cy(clk)
ns
t
h(DYCS)
DYCS hold time 0.3 + 0.5 T
cy(clk)
0.9 + 0.5 T
cy(clk)
-ns
t
d(RASV)
row address strobe valid delay time - 3.1 + 0.5 T
cy(clk)
4.9 + 0.5 T
cy(clk)
ns
t
h(RAS)
row address strobe hold time 0.5 + 0.5 T
cy(clk)
1.1 + 0.5 T
cy(clk)
-ns
t
d(CASV)
column address strobe valid delay time - 2.9 + 0.5 T
cy(clk)
4.6 + 0.5 T
cy(clk)
ns
t
h(CAS)
column address strobe hold time 0.3 + 0.5 T
cy(clk)
0.9 + 0.5 T
cy(clk)
-ns
t
d(WEV)
WE valid delay time - 3.2 + 0.5 T
cy(clk)
5.9 + 0.5 T
cy(clk)
ns
t
h(WE)
WE hold time 1.3 + 0.5 T
cy(clk)
1.4 + 0.5 T
cy(clk)
-ns
t
d(DQMOUTV)
DQMOUT valid delay time - 3.1 + 0.5 T
cy(clk)
5.0 + 0.5 T
cy(clk)
ns
t
h(DQMOUT)
DQMOUT hold time 0.2 + 0.5 T
cy(clk)
0.8 + 0.5 T
cy(clk)
-ns
t
d(AV)
address valid delay time - 3.8 + 0.5 T
cy(clk)
6.3 + 0.5 T
cy(clk)
ns
t
h(A)
address hold time 0.3 + 0.5 T
cy(clk)
0.9 + 0.5 T
cy(clk)
-ns
t
d(CKEOUTV)
CKEOUT valid delay time - 3.1 + 0.5 T
cy(clk)
5.1 + 0.5 T
cy(clk)
ns
t
h(CKEOUT)
CKEOUT hold time 0.5 T
cy(clk)
0.7 + 0.5 T
cy(clk)
-ns
Read cycle parameters
t
su(D)
data input set-up time 1.5 0.5 - ns
t
h(D)
data input hold time - 0.8 2.2 ns
Write cycle parameters
t
d(QV)
data output valid delay time - 3.8 + 0.5 T
cy(clk)
6.2 + 0.5 T
cy(clk)
ns
t
h(Q)
data output hold time 0.5 T
cy(clk)
0.7 + 0.5 T
cy(clk)
-ns
Table 27. Dynamic characteristics: Dynamic external memory interface; EMC_CLK[3:0]
delay values
T
amb
=
40
C to 85
C; V
DD(IO)
=3.3 V
10 %; 2.2 V
V
DD(REG)(3V3)
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
t
d
delay time delay value
CLKn_DELAY = 0
[1]
0.0 0.0 0.0 ns
CLKn_DELAY = 1
[1]
0.4 0.5 0.8 ns
CLKn_DELAY = 2
[1]
0.7 1.0 1.7 ns
CLKn_DELAY = 3
[1]
1.1 1.6 2.5 ns
CLKn_DELAY = 4
[1]
1.4 2.0 3.3 ns
CLKn_DELAY = 5
[1]
1.7 2.6 4.1 ns
CLKn_DELAY = 6
[1]
2.1 3.1 4.9 ns
CLKn_DELAY = 7
[1]
2.5 3.6 5.8 ns