Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 125 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
Table 30. Dynamic characteristics: Ethernet
T
amb
=  40  C to 85  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V. Values guaranteed by
design.
Symbol Parameter Conditions Min Max Unit
RMII mode
f
clk
clock frequency for ENET_RX_CLK
[1]
-50MHz

clk
clock duty cycle
[1]
50 50 %
t
su
set-up time for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
4- ns
t
h
hold time for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
2- ns
MII mode
f
clk
clock frequency for ENET_TX_CLK
[1]
- 25 MHz

clk
clock duty cycle
[1]
50 50 %
t
su
set-up time for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2]
4- ns
t
h
hold time for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2]
2- ns
f
clk
clock frequency for ENET_RX_CLK
[1]
- 25 MHz

clk
clock duty cycle
[1]
50 50 %
t
su
set-up time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
4- ns
t
h
hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2]
2- ns
Fig 37. Ethernet timing
002aag210
t
h
t
su
ENET_RX_CLK
ENET_TX_CLK
ENET_RXD[n]
ENET_RX_DV
ENET_RX_ER
ENET_TXD[n]
ENET_TX_EN
ENET_TX_ER