Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 149 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
18. Revision history
Table 42. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC4350_30_20_10 v.4.2 20140818 Product data sheet LPC4350_30_20_10 v.4.1
Modifications:
• Parameter C
I
corrected for high-drive pins (changed from 2 pF to 5.2 pF). See
Table 10.
• Table 18 “Dynamic characteristic: I/O pins
[1]
” added.
• IRC accuracy changed from 1 % to 1.5 % over the full temperature range. See Table
16 “Dynamic characteristic: IRC oscillator”.
• Description of internal pull-up resistor configuration added for RESET, WAKEUPn,
and ALARM pins.See Table 3
.
• Description of DEBUG pin updated.
• Input range for PLL1 corrected: 1 MHz to 25 MHz. See Section 7.22.7 “System PLL1”.
• Section 13.7 “Suggested USB interface solutions” added.
• SSP master mode timing diagram updated with SSEL timing parameters. See Figure
30 “SSP master mode timing (SPI mode)”.
• Parameters t
lead
, t
lag
, and t
d
added in Table 22 “Dynamic characteristics: SSP pins in
SPI mode”.
• Reset state of the RTC alarm pin RTC_ALARM added. See Table 3.
• SRAM location for parts LPC4320 corrected in Figure 7.
• IEEE standard 802.3 compliance added to Section 11.16. Covers Ethernet dynamic
characteristics of ENET_MDIO and ENET_MDC signals.\
• Signal polarity of EMC_CKEOUT and EMC_DQMOUT corrected. Both signals are
active HIGH.
• SPIFI output timing parameters in Tabl e 33 corrected to apply to Mode 0:
– t
v(Q)
changed to 3.2 ns.
– t
h(Q)
changed to 0.2 ns,
• Parameter t
CSLWEL
with condition PB = 1 corrected: (WAITWEN + 1)  T
cy(clk)
added.
See Table 25 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Parameter t
CSLBLSL
with condition PB = 0 corrected: (WAITWEN + 1)  T
cy(clk)
added.
See Table 25 “Dynamic characteristics: Static asynchronous external memory
interface”.
LPC4350_30_20_10 v.4.1 20131211 Product data sheet - LPC4350_30_20_10 v.4
Modifications:
• Description of RESET pin updated in Table 3.
• Layout of local SRAM at address 0x1008 0000 clarified in Figure 7
“LPC4350/30/20/10 Memory mapping (overview)”.
• Maximum value for V
i(RMS)
added in Section 13.3 “RTC oscillator”.
• V
O
for RTC_ALARM pin added in Table 10.
• RTC_ALARM and WAKEUPn pins added to Table 10.
• Table note 9 added in Table 10.
• Timing parameters in Table 31 “Dynamic characteristics: SD/MMC” corrected.
• Band gap characteristics removed.
• OTP memory size available for general purpose use corrected.
• Part LPC4350FBD208 removed.
LPC4350_30_20_10 v.4 20130326 Product data sheet - LPC4350_30_20_10 v.3.7